Motor position at the last encoder index. This latched encoder value correlates to the encoder counter value presented in "Encoder position" (DataID 12202).  The raw, unprocessed encoder value latched by the FPGA is presented in the "Raw encoder counts at index" (DataID 12225). See the "Incremental encoder hardware configuration" (DataID 10220) for how to specify the A/B/Z pattern that constitutes a encoder index.

Position delta between indices. If the encoder is operating properly, this value will be a multiple of the encoder counts between indices (DataID 10205).

The accumulated index skew counts. If the skew amount exceeds skew limit then an error will be triggered.

Total # of index noise spikes within an encoder revolution. This value is cleared when a new (valid) index occurs.

This is the encoder hardware status register. The bit definitions are as follows:

   bit 0 - zero index latched.  When this bit is set, it will remain on for approximately 4 msec and then be automatically cleared by the servo code.
   bit 1 - raw encoder channel A signal state
   bit 2 - raw encoder channel B signal state
   bit 3 - raw index channel signal state
   bit 4 - encoder quadrature error flag
   bit 5:7 - (reserved)
   bit 8 - index error detected for Precise absolute encoder
   bit 9 - Precise absolute encoder index latch direction, 0=positive, 1=negative
   bit 10:15 - (reserved)

This is the raw (unprocessed) encoder counter that was latched by the FPGA when the last encoder index was detected. Normally, the "Motor position at index" (DataID 12220) should be referenced since that value directly correlates to the encoder counter reported by the "Encoder position" (DataID 12202).